U.S. Pat. No. 6,608,366 (Patent Document 1) describes a semiconductor device of such a type that each of a plurality of leads is exposed on a mounting surface side of a package. Also, each of the plurality of leads described in Patent Document 1 has a recess formed at a peripheral part of the mounting surface.
Also, Japanese Patent Application Laid-Open Publication No. 2000-294719 (Patent Document 2) describes a semiconductor device in which concave parts are formed on terminal connecting surfaces of a plurality of leads and in which solder is buried in the concave parts.
Further, Japanese Patent Application Laid-Open Publication No. 2005-19240 (Patent Document 3) describes a semiconductor device in which concave parts are formed on a peripheral part side of leads formed on a back surface side of a resin sealing body and in which a plating layer is formed on inner wall surfaces of the concave parts.
Still further, Japanese Patent Application Laid-Open Publication No. 2008-112961 (Patent Document 4) describes a method of manufacturing a semiconductor device which forms a trench in a frame part of a lead frame along a dicing line by using a dicing saw, and then, forms a plating layer in the trench, and then, penetrates through and removes the frame part and a sealing resin by using a dicing saw having a narrower width than that of the trench.
Still further, Japanese Patent Application Laid-Open Publication No. 2005-93559 (Patent Document 5) describes a method of manufacturing a semiconductor package which forms a via hole that is a long hole at an outer peripheral part of each lead, and the via hole is cut by a cutting line that cuts it by half after a lead frame is sealed with resin. Patent Document 5 also describes that a fillet-promoting corner part is formed at an outer peripheral part of a bottom end surface of the semiconductor package.